indent/pretty-printing utility for System Verilog

indent/pretty-printing utility for System Verilog

Not properly a programming question, but is anybody aware of a open source
indent (similar to gnu indent or astyle) capable of indenting System
Verilog?
More sophisticated pretty-printing (such as aligning assignments or
reformatting source to fit 80 character lines) would be very nice to have,
but basic indentation would already be useful.